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3.2 gbps quad buffer mux/demux AD8159 rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2006 analog devices, inc. all rights reserved. features port level 2:1 mux/1:2 demux each port consists of 4 lanes each lane runs from dc to 3.2 gbps, independent of the other lanes compensates over 40 inches of fr4 at 3.2 gbps through two levels of input equalization, or four levels of output pre-emphasis accepts ac- or dc-coupled differential cml inputs low deterministic jitter, typically 20 ps p-p low random jitter, typically 1 ps rms ber < 10 -16 on-chip termination reversible inputs and outputs on one port unicast or bicast on 1:2 demux function port level loopback capability single lane switching capability 3.3 v core supply flexible i/o supply down to 2.5 v low power, typically 1 w in basic configuration 100-pin tqfp_ep ?40c to +85c operating temperature range applications low cost redundancy switch sonet oc48/sdh16 and lower data rates xaui (10 gigabit ethernet) over backplane gigabit ethernet over backplane fibre channel 1.06 gbps and 2.125 gbps over backplane infiniband over backplane pci-express over backplane general description the AD8159 is an asynchronous, protocol agnostic, quad-lane 2:1 switch with a total of 12 differential pecl/cml-compatible inputs and 12 differential cml outputs. the operation of this product is optimized for nrz signaling with data rates up to 3.2 gbps per lane. each lane offers two levels of input equalization and four levels of output pre-emphasis. the AD8159 consists of four multiplexers and four demulti- plexers, one per lane. each port is a 4-lane link, and each lane runs up to a 3.2 gbps data rate independent of the other lanes. the lanes are switched independently using the four select pins, sel[3:0]; each select pin controls one lane of the port. the AD8159 has low latency and very low lane-to-lane skew. functional block diagram 05611-001 in_b[3:0] out_b[3:0] transmit pre- emphasis quad 2:1 multiplexer/ 1:2 demultiplexer receive equalization control logic transmit pre- emphasis receive equalization i/o cross- over switch out_c[3:0]/ in_c[3:0] in_c[3:0]/ out_c[3:0] lb_a lb_b lb_c pe_a[1:0] pe_b[1:0] pe_c[1:0] eq_a eq_b eq_c sel[3:0] bicast reverse_c out_a[3:0] in_a[3:0] 2:1 1:2 eq eq eq AD8159 figure 1. the main application of the AD8159 is to support redundancy on both the backplane side and the line interface side of a serial link. the device has unicast and bicast capability, so it is configurable to support either 1 + 1 or 1:1 redundancy. the AD8159 supports reversing the output and input pins on one of its ports, which helps to connect two asics with opposite pinouts. the AD8159 is also used for testing high speed serial links by duplicating incoming data and sending it to the destination port and to test equipment simultaneously.
AD8159 rev. a | page 2 of 24 table of contents features .............................................................................................. 1 applications....................................................................................... 1 general description ......................................................................... 1 functional block diagram .............................................................. 1 revision history ............................................................................... 2 specifications..................................................................................... 3 absolute maximum ratings............................................................ 4 esd caution.................................................................................. 4 pin configuration and function descriptions............................. 5 typical performance characteristics ............................................. 7 evaluation board simplified block diagrams ............................ 12 test circuits..................................................................................... 13 theory of operation ...................................................................... 15 input equalization (eq) and output pre-emphasis (pe) .... 15 loopback ..................................................................................... 16 port c reverse (crossover) capability.................................... 17 applications..................................................................................... 18 interfacing to the AD8159............................................................. 19 termination structures.............................................................. 19 input compliance....................................................................... 19 output compliance ................................................................... 20 outline dimensions ....................................................................... 22 ordering guide .......................................................................... 22 revision history 4/06rev. 0 to rev. a changes to applications section .................................................... 1 changes to table 5.......................................................................... 15 updates to outline dimensions ................................................... 22 changes to ordering guide .......................................................... 22 9/05revision 0: initial version
AD8159 rev. a | page 3 of 24 specifications v cc = +3.3 v, v ee = 0 v, r l = 50 , basic configuration, 1 data rate= 3.2 gbps, input common-mode voltage = 2.7 v, differential input swing = 800 mv p-p, @ t a = +25c, unless otherwise noted. table 1. parameter conditions min typ max unit dynamic performance data rate/channel (nrz) dc 3.2 gbps deterministic jitter data rate = 3.2 gbps; see figure 21 20 ps p-p random jitter rms; see figure 24 1 ps propagation delay input to output 600 ps lane-to-lane skew 100 ps switching time 5 ns output rise/fall time 20% to 80% 100 ps input characteristics input voltage swing differential, v icm = v cc ? 0.6 v; 2 see figure 22 200 2000 mv p-p input voltage range common mode, v id = 800 mv p-p; 3 see figure 25 v ee + 1.8 v cc + 0.3 v input bias current 4 a input capacitance 2 pf output characteristics output voltage swing differential, pe = 0 800 mv p-p output voltage range single-ended absolute voltage level; see figure 26 v cc ? 1.6 v cc + 0.6 v output current port a/b, pe_a/b = 0 16 ma port c, pe_c = 0 20 ma port a/b, pe_a/b = 3 28 ma port c, pe_c = 3 32 ma output capacitance 2 pf termination characteristics resistance differential 90 100 110 temperature coefficient 0.15 /c power supply operating range v cc v ee = 0 v 3.0 3.3 3.6 v 175 ma supply current i cc i i/o = i tto + i ttoi + i tti + i ttio basic configuration 1 , dc-coupled inputs/outputs, 400 mv i/o swings (800 mv p-p differential), 50 far end terminations 144 ma 255 ma supply current i cc i i/o = i tto + i ttoi + i tti + i ttio bicast = 1, pe = 3 on all ports, dc-coupled inputs/outputs, 400 mv i/o swings (800 mv p-p differential), 50 far end terminations 352 ma thermal characteristics operating temperature range ?40 +85 c ja still air 29 c/w jb still air 16 c/w jc still air 13 c/w logic input characteristics input high (v ih ) 2.4 v cc v input low (v il ) v ee 0.8 v 1 bicast off, loopback off on all ports, pre-emphasis off on all ports, equalization set to minimum on all ports. 2 v icm = input common-mode voltage. 3 v id = input differential peak-to-peak voltage swing.
AD8159 rev. a | page 4 of 24 absolute maximum ratings table 2. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. parameter rating v cc to v ee 3.7 v v tti v cc + 0.6 v v ttio v cc + 0.6 v v tto v cc + 0.6 v v ttoi v cc + 0.6 v internal power dissipation 4.26 w differential input voltage 2.0 v logic input voltage v ee ? 0.3 v < v in < v cc + 0.6 v storage temperature range ?65 c to +125 c lead temperature 300 c esd caution esd (electrostatic discharge) sensitive device. electros tatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge wi thout detection. although this product features proprietary esd protection circuitry, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd pr ecautions are recommended to avoid performance degradation or loss of functionality.
AD8159 rev. a | page 5 of 24 pin configuration and fu nction descriptions 74 eq_a 73 eq_b 72 eq_c 69 sel1 70 sel2 71 sel3 75 v cc 68 sel0 67 lb_c 66 lb_b 64 bicast 63 v cc 62 ip_b0 61 in_b0 60 v ee 59 ip_b1 58 in_b1 57 v tti 56 ip_b2 55 in_b2 54 v ee 53 ip_b3 52 in_b3 51 v cc 65 lb_a pin 1 nc = no connect 100 v cc 99 oip_c0 98 oin_c0 97 v ee 96 oip_c1 95 oin_c1 94 v ttoi 93 oip_c2 92 oin_c2 91 v ee 90 oip_c3 89 oin_c3 88 v cc 87 iop_c0 86 ion_c0 85 v ee 84 iop_c1 83 ion_c1 82 v ttio 81 iop_c2 80 ion_c2 79 v ee 78 iop_c3 77 ion_c3 76 v cc 26 v cc 27 in_a3 28 ip_a3 29 v ee 30 in_a2 31 ip_a2 32 v tti 33 in_a1 34 ip_a1 35 v ee 36 in_a0 37 ip_a0 38 v cc 39 on_b3 40 op_b3 41 v ee 42 on_b2 43 op_b2 44 v tto 45 on_b1 46 op_b1 47 v ee 48 on_b0 49 op_b0 50 v cc 2 v cc 3 v ee 4 v ee 7 pe_a1 6 pe_a0 5 v ee 1 nc 8 pe_b0 9 pe_b1 10 pe_c0 12 reverse_c 13 v cc 14 on_a3 15 op_a3 16 v ee 17 on_a2 18 op_a2 19 v tto 20 on_a1 21 op_a1 22 v ee 23 on_a0 24 op_a0 25 v cc 11 pe_c1 AD8159 top view (not to scale) 05611-002 notes 1. the AD8159 tqfp has an exposed paddle (epad) on the underside of the package which aids in heat dissipation. the epad must be electrically connected to the v ee supply plane in order to meet thermal specifications. figure 2. pin configuration table 3. pin function descriptions pin no. mnemonic type description 1 nc n/a no connect 2, 13, 25, 26, 38, 50, 51, 63, 75, 76, 88, 100 v cc power positive supply 3 to 5, 16, 22, 29, 35, 41, 47, 54, 60, 79, 85, 91, 97 v ee power negative supply 6 pe_a0 control pre-emphasis control for port a (lsb) 7 pe_a1 control pre-emphasis control for port a (msb) 8 pe_b0 control pre-emphasis control for port b (lsb) 9 pe_b1 control pre-emphasis control for port b (msb) 10 pe_c0 control pre-emphasis control for port c (lsb) 11 pe_c1 control pre-emphasis control for port c (msb) 12 reverse_c control reverse in puts and outputs on port c 14 on_a3 i/o high speed output complement 15 op_a3 i/o high speed output 17 on_a2 i/o high speed output complement 18 op_a2 i/o high speed output 19, 44 v tto power port a and port b output termination supply 20 on_a1 i/o high speed output complement 21 op_a1 i/o high speed output 23 on_a0 i/o high speed output complement 24 op_a0 i/o high speed output 27 in_a3 i/o high speed input complement
AD8159 rev. a | page 6 of 24 pin no. mnemonic type description 28 ip_a3 i/o high speed input 30 in_a2 i/o high speed input complement 31 ip_a2 i/o high speed input 32, 57 v tti power port a and port b input termination supply 33 in_a1 i/o high speed input complement 34 ip_a1 i/o high speed input 36 in_a0 i/o high speed input complement 37 ip_a0 i/o high speed input 39 on_b3 i/o high speed output complement 40 op_b3 i/o high speed output 42 on_b2 i/o high speed output complement 43 op_b2 i/o high speed output 45 on_b1 i/o high speed output complement 46 op_b1 i/o high speed output 48 on_b0 i/o high speed output complement 49 op_b0 i/o high speed output 52 in_b3 i/o high speed input complement 53 ip_b3 i/o high speed input 55 in_b2 i/o high speed input complement 56 ip_b2 i/o high speed input 58 in_b1 i/o high speed input complement 59 ip_b1 i/o high speed input 61 in_b0 i/o high speed input complement 62 ip_b0 i/o high speed input 64 bicast control bicast enable 65 lb_a control loopback enable for port a 66 lb_b control loopback enable for port b 67 lb_c control loopback enable for port c 68 sel0 control a /b select for lane 0 69 sel1 control a /b select for lane 1 70 sel2 control a /b select for lane 2 71 sel3 control a /b select for lane 3 72 eq_c control equalization control for port c 73 eq_b control equalization control for port b 74 eq_a control equalization control for port a 77 ion_c3 i/o high speed input/output complement 78 iop_c3 i/o high speed input/output 80 ion_c2 i/o high speed input/output complement 81 iop_c2 i/o high speed input/output 82 v ttio power port c input/output termination supply 83 ion_c1 i/o high speed input/output complement 84 iop_c1 i/o high speed input/output 86 ion_c0 i/o high speed input/output complement 87 iop_c0 i/o high speed input/output 89 oin_c3 i/o high speed output/input complement 90 oip_c3 i/o high speed output/input 92 oin_c2 i/o high speed output/input complement 93 oip_c2 i/o high speed output/input 94 v ttoi power port c output/input termination supply 95 oin_c1 i/o high speed output/input complement 96 oip_c1 i/o high speed output/input 98 oin_c0 i/o high speed output/input complement 99 oip_c0 i/o high speed output/input
AD8159 rev. a | page 7 of 24 typical performance characteristics v cc = +3.3 v, v ee = 0 v, r l = 50 , basic configuration, data rate = 3.2 gbps, in put common-mode voltage = 2.7 v, differential input swing = 800 mv p-p, t a = 25c, unless otherwise noted. note: all graphs were generated using the setup shown in figure 32 , unless otherwise specified. 0 ?16 0 1.0 05611-006 time (unit interval) bit error rate (decades) ?2 ?4 ?6 ?8 ?10 ?12 ?14 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 05611-003 150mv/div 39.0625ps/div figure 6. output port a bathtub curve 3.2 gbps figure 3. output port a eye diagram 3.2 gbps input port a or input port c 0 ?16 0 1.0 05611-007 time (unit interval) bit error rate (decades) ?2 ?4 ?6 ?8 ?10 ?12 ?14 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 05611-004 150mv/div 39.0625ps/div figure 7. output port b bathtub curve 3.2 gbps figure 4. output port b eye diagram input port b or input port c 0 ?16 01 05611-008 time (unit interval) bit error rate (decades) . 0 ?2 ?4 ?6 ?8 ?10 ?12 ?14 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 05611-005 150mv/div 39.0625ps/div figure 5. output port c eye diagram 3.2 gbps input port a or input port b figure 8. output port c bathtub curve 3.2 gbps
AD8159 rev. a | page 8 of 24 05611-012 150mv/div 39.0625ps/div 05611-009 150mv/div 39.0625ps/div figure 9. eye diagram over backplane (18 fr4 + 2 gbx connectors), pe = 0 figure 12. eye diagram over backplane (18 fr4 + 2 gbx connectors), pe = 1 05611-044 150mv/div 39.0625ps/div 05611-013 150mv/div 39.0625ps/div figure 10. eye diagram over backplane (30 fr4 + 2 gbx connectors), pe = 0 figure 13. eye diagram over backplane (30 fr4 + 2 gbx connectors), pe = 2 05611-014 150mv/div 39.0625ps/div 05611-011 150mv/div 39.0625ps/div figure 11. eye diagram over backplane (36 fr4 + 2 gbx connectors), pe = 0 figure 14. eye diagram over backplane (36 fr4 + 2 gbx connectors), pe = 3
AD8159 rev. a | page 9 of 24 05611-018 150mv/div 39.0625ps/div 05611-015 150mv/div 39.0625ps/div figure 15. eye diagram over backplane (42 fr4 + 2 gbx connectors), pe = 0 figure 18. eye diagram over backplane (42 fr4 + 2 gbx connectors), pe = 3 05611-005 150mv/div 39.0625ps/div 05611-016 150mv/div 39.0625ps/div figure 16. reference eye diagram for figure 19 figure 19. eye diagram with equalization (10 fr4), eq = 0 note: see figure 34 for test circuit used 05611-044 150mv/div 39.0625ps/div 05611-019 150mv/div 39.0625ps/div figure 17. reference eye diagram for figure 20. eye diagram with equalization (34 fr4 + 2 gbx connectors), eq = 1 note: see figure 20 figure 34 for test circuit used
AD8159 rev. a | page 10 of 24 ?2ps 0s ?3ps 3ps 05611-020 2ps ?1ps 1ps 100 0 1.0 3.6 05611-021 data rate (gbps) deterministic jitter (ps) 90 80 70 60 50 40 30 20 10 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 figure 24. random jitter histogram note: see figure 21. deterministic jitter vs. data rate figure 35 for test circuit used 100 0 04 05611-023 input common-mode voltage (v) deterministic jitter (ps) 100 0 0 2000 05611-024 differential input swing (mv p-p) deterministic jitter (ps) 90 80 70 60 50 40 30 20 10 200 400 600 800 1000 1200 1400 1600 1800 input c input a/b vicm = 2.7v . 0 90 80 70 60 50 40 30 20 10 0.5 1.0 1.5 2.0 2.5 3.0 3.5 differential input swing = 800mv p-p input a/b input c figure 22. deterministic jitte r vs. differential input swing figure 25. deterministic jitter vs. input common-mode voltage 100 0 1.8 4.0 05611-025 v cc (v) deterministic jitter (ps) 90 80 70 60 50 40 30 20 10 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 input c input a/b 100 0 2.0 4.0 05611-026 output termination voltage (v) deterministic jitter (ps) 90 80 70 60 50 40 30 20 10 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 output c output a/b figure 23. deterministic ji tter vs. core supply voltage figure 26. deterministic jitter vs. output termination voltage
AD8159 rev. a | page 11 of 24 100 0 ?60 100 05611-022 temperature (c) deterministic jitter (ps) 90 80 70 60 50 40 30 20 10 ?40?200 20406080 120 0 ?60 100 05611-027 temperature (c) transition time (ps) 100 80 60 40 20 ?40?200 20406080 figure 27. deterministic jitter vs. temperature figure 28. transition time vs. temperature note: see figure 33 for test circuit used
AD8159 rev. a | page 12 of 24 evaluation board simplified block diagrams 05611-028 AD8159 input a output c v tti / v ttio v cc v tto / v ttoi v ee 3.3v AD8159-eval-ac ac-coupled evaluation board input b input c output a output b a b c c a b AD8159 ac-coupled evaluation board 5" 5" 100 ? diff. trace 100 ? diff. trace 100 ? diff. trace 0.1f 0.1f 0.1f 100? diff. trace 0.1f 100? diff. trace 0.1f 100? diff. trace 0.1f figure 29. ac-coupled evaluation board simplified block diagram 05611-029 AD8159 input a output c v tti / v ttio v cc v tto / v ttoi v ee AD8159-eval-dc dc-coupled evaluation board input b input c output a output b a b c c a b AD8159 dc-coupled evaluation board 5" 5" ?3.3v 100? diff. trace 100? diff. trace 100? diff. trace 100? diff. trace 100? diff. trace 100? diff. trace figure 30. dc-coupled evaluation board simplified block diagram
AD8159 rev. a | page 13 of 24 test circuits all graphs were generated using the setup shown in figure 32 , unless otherwise specified. 05611-030 0.25" teradyne fr4 test backplane differential stripline traces 8mm wide, 8mm space, 8mm height t race lengths = 6", 18", 24", 30" + 3" 2 daughter cards gbx4 to sma daughter cards figure 31. test backplane 05611-031 a b c c a b AD8159 ac-coupled evaluation board test backplane 50 ? 50? high speed real-time oscilloscope 50? 50? cable 50? cable 50 ? cable pattern generator data out notes 1. single-ended representation figure 32. ac-coupled test circuit 05611-032 a b c c a b AD8159 dc-coupled evaluation board test backplane 50 ? 50? high speed real-time oscilloscope 50? 50? cable 50? cable 50 ? cable pattern generator data out notes 1. single-ended representation figure 33. dc-coupled test circuit note: test circuit used for figure 28
AD8159 rev. a | page 14 of 24 05611-033 a b c c a b AD8159 dc-coupled evaluation board test backplane 50 ? 50? 50? cable 50 ? cable 50? cable pattern generator data out high speed real-time oscilloscope 50? a b c c a b AD8159 dc-coupled evaluation board 50 ? 50? 50? cable notes 1. single-ended representation device under test figure 34. equalization test circuit note: test circuit used for figure 19 and figure 20 05611-034 50? cable pattern generator data out high speed sampling oscilloscope 50? a b c c a b AD8159 ac-coupled evaluation board 50? cable notes 1. single-ended representation 50? 50? figure 35. random jitter test circuit note: test circuit used for figure 24
AD8159 rev. a | page 15 of 24 theory of operation the AD8159 relays received data on the demultiplexer input port c to output port a and/or output port b, depending on the mode selected by the bicast control pin. on the multiplexer side, the AD8159 relays received data on either input port a or input port b to output port c, based on the sel[3:0] pin states. the AD8159 is configured by toggling control pins. on the demul- tiplexer side, when the device is configured in the unicast mode, it sends the received data on input port c to output port a or output port b. when the device is configured in the bicast mode, received data on input port c is sent to both output port a and output port b. on the multiplexer side, only received data on input port a or input port b is sent to output port c, depending on the state of the sel[3:0] pins. table 4 summarizes port selection and configuration when loopback is disabled (lb_a = lb_b = lb_c = 0). when the device is in unicast mode, the output lanes on either port a or port b are in an idle state. in the idle state, the output tail current is set to 0, and the p and n sides of the lane are pulled up to the output termination voltage through the on-chip termination resistors. table 4. port selection and configuration table sel bicast out_a out_b out_c 0 0 in_c idle in_a 0 1 in_c in_c in_a 1 0 idle in_c in_b 1 1 in_c in_c in_b input equalization (eq) and output pre-emphasis (pe) in backplane applications, th e AD8159 needs to compensate for signal degradation over potentially long traces. the device supports two levels of input equa lization, configured on a per- port basis. table 6 to table 8 summarize the high-frequency gain (eq) for each control settin g as well as the typical length of backplane trace that can be compensated for each setting. the AD8159 also has four levels of output pre-emphasis, configured for each port. the pre-emphasis circuitry adds a controlled amount of overshoot to the output waveform to compensate for the loss in a backplane trace. table 9 to tabl e 11 summarize the high-frequency gain, amount of overshoot, and the typical backplane channel length (including two connectors) that can be compensated using each setting. a typical backplane is made of fr4 material with 8 mil wide trace and 8 mil spacing loosely coupled differential traces. each backplane channel consists of two connectors. the total length of the channel includes three inches of traces on each card. table 5. port c i/o selection port c hen reverse_c 0 port c hen reverse_c 1 port c pin list on 100-lead tfp pin name input/output pin name input/output 77 ion_c3 = inn_c3 input pin ion_c3 = outn_c3 output pin 78 iop_c3 = inp_c3 input pin iop_c3 = outp_c3 output pin 80 ion_c2 = inn_c2 input pin ion_c2 = outn_c2 output pin 81 iop_c2 = inp_c2 input pin iop_c2 = outp_c2 output pin 83 ion_c1 = inn_c1 input pin ion_c1 = outn_c1 output pin 84 iop_c1 = inp_c1 input pin iop_c1 = outp_c1 output pin 86 ion_c0 = inn_c0 input pin ion_c0 = outn_c0 output pin 87 iop_c0 = inp_c0 input pin iop_c0 = outp_c0 output pin 89 oin_c3 = outn_c3 output pin oin_c3 = inn_c3 input pin 90 oip_c3 = outp_c3 output pin oip_c3 = inp_c3 input pin 92 oin_c2 = outn_c2 output pin oin_c2 = inn_c2 input pin 93 oip_c2 = outp_c2 output pin oip_c2 = inp_c2 input pin 95 oin_c1 = outn_c1 output pin oin_c1 = inn_c1 input pin 96 oip_c1 = outp_c1 output pin oip_c1 = inp_c1 input pin 98 oin_c0 = outn_c0 output pin oin_c0 = inn_c0 input pin 99 oip_c0 = outp_c0 output pin oip_c0 = inp_c0 input pin
AD8159 rev. a | page 16 of 24 table 6. in_c port input equalization settings table 10. out_a port output pre-emphasis settings eq_c eq typical backplane length typical backplane length 0 6 db 0 to 20 inches pe_a[1] pe_a[0] pe overshoot 1 12 db 20 to 40+ inches 0 0 0 db 0% 0 to 10 inches table 7. in_a port input equalization settings eq_a eq typical backplane length 0 6 db 0 to 20 inches 1 12 db 20 to 40+ inches table 8. in_b port input equalization settings eq_b eq typical backplane length 0 6 db 0 to 20 inches 1 12 db 20 to 40+ inches table 9. out_c port output pre-emphasis settings pe_c[1] pe_c[0] pe overshoot typical backplane length 0 0 0 db 0% 0 to 10 inches 0 1 1.9 db 15% 10 to 20 inches 1 0 3.5 db 35% 20 to 30 inches 1 1 4.9 db 60% 30 to 40+ inches 0 1 1.9 db 15% 10 to 20 inches 1 0 3.5 db 35% 20 to 30 inches 1 1 4.9 db 60% 30 to 40+ inches table 11. out_b port output pre-emphasis settings typical backplane length pe_b[1] pe_b[0] pe overshoot 0 0 0 db 0% 0 to 10 inches 0 1 1.9 db 15% 10 to 20 inches 1 0 3.5 db 35% 20 to 30 inches 1 1 4.9 db 60% 30 to 40+ inches loopback the AD8159 also supports port level loopback, illustrated in figure 36 . the loopback control pins override the lane select (sel[3:0]) and bicast control (bicast) pins. table 12 summa- rizes the different loopback configurations. 05611-035 x4 x4 x4 x4 x4 x4 1:2 demux out_a[3:0] out_b[3:0] in_b[3:0] in_a[3:0] port c loopbac k port a loopback port b loopback 2:1 mux in_c[3:0] out_c[3:0] figure 36. port-based loopback capability
AD8159 rev. a | page 17 of 24 table 12. loopback, bicast, and port select settings 1 lb_a lb_b lb_c sel bicast out_a out_b out_c 0 0 0 0 0 in_c idle in_a 0 0 0 0 1 in_c in_c in_a 0 0 0 1 0 idle in_c in_b 0 0 0 1 1 in_c in_c in_b 0 0 1 0 0 in_c idle in_c 0 0 1 x 1 in_c in_c in_c 0 0 1 1 0 idle in_c in_c 0 1 0 0 x in_c in_b in_a 0 1 0 1 0 idle in_b in_b 0 1 0 1 1 in_c in_b in_b 0 1 1 0 x in_c in_b in_c 0 1 1 1 0 idle in_b in_c 0 1 1 x 1 in_c in_b in_c 1 0 0 0 0 in_a idle in_a 1 0 0 0 1 in_a in_c in_a 1 0 0 1 x in_a in_c in_b 1 0 1 0 0 in_a idle in_c 1 0 1 x 1 in_a in_c in_c 1 0 1 1 x in_a in_c in_c 1 1 0 0 x in_a in_b in_a 1 1 0 1 x in_a in_b in_b 1 1 1 x x in_a in_b in_c 1 switching is done on a lane-by-lane basis, but input equalization, output pre-emphasis, and loopback are set for each port. port c reverse (crossover) capability 05611-036 x4 x4 x4 x4 x4 x4 1:2 demux out_a[3:0] out_b[3:0] in_b[3:0] in_a[3:0] x4 reverse_c 2:1 mux in_c [3:0]/out_c[3:0] x4 out_c [3:0]/in_c[3:0] i/o switch i/o switch port c has a reversible i/o capability. the sense (input vs. output) of the port c pins can be swapped by toggling the reverse_c control pin. this feature has been added to facilitate the connection to different asics that may have the opposite pinouts. figure 37 illustrates the reversible i/o function of port c, and table 5 describes this function in a selection table that corresponds to a tqfp-100 package. please note that the reverse capability is supported only on port c. figure 37. port c reverse i/o capability
AD8159 rev. a | page 18 of 24 applications the main application of the AD8159 is to support redundancy on both the backplane side and the line interface side of a serial link. each port consists of four lanes to support standards such as xaui. another application for the AD8159 is test equipment for evaluating high speed serial i/os running at data rates at or lower than 3.2 gbps. figure 40 illustrates a possible application of the AD8159 in a simple xaui link tester. figure 38 illustrates redundancy in an xaui backplane system. each line card is connected to two switch fabrics (primary and redundant). the device can be configured to support either 1 + 1 or 1:1 redundancy. fabric cards line cards backplane AD8159 physical interface macs framers fabric interface traffic managers network processor AD8159 physical interface macs framers fabric interface traffic managers network processor 05611-037 redundant switch fabric primary switch fabric figure 38. using the AD8159 for switch redundancy line card macs framers fabric interface traffic managers network processor primary module 05611-038 redundant module figure 39. using the AD8159 for line interface redundancy port b port a port c fpga generates simple patterns connector connect to device under test test card connector 05611-039 connect to protocol analyzer figure 40. using the AD8159 in test equipment
AD8159 rev. a | page 19 of 24 interfacing to the AD8159 termination structures for output ports, there are two 50 resistors connected to the termination supply. note that the differential input resistance for both structures is the same, 100 . to determine the best strategy for connecting to the high speed pins of the AD8159, the user must first be familiar with the on- chip termination structures. the AD8159 contains two types of these structures (see input compliance figure 41 and figure 42 ): one type for input and bidirectional ports and one type for output ports. the range of allowable input voltages is determined by the fundamental limitations of the active input circuitry. this range of signals is normally a function of the common-mode level of the input signal, the signal swing, and the supply voltage. for a given input signal swing, there is a range of common-mode voltages that keeps the high and low voltage excursions within acceptable limits. similarly, for a given common-mode input voltage there is a maximum acceptable input signal swing. there is also a minimum signal swing that the active input circuitry can resolve reliably. 05611-040 54.5 ? 54.5 ? 1173? v tti /v ttio /v ttoi n p figure 41. termination structure: input and bidirectional ports 05611-041 50? 50? v tto pn figure 22 and figure 25 summarize the input voltage ranges for all ports. note that the input range is different when comparing bidirectional ports to strictly input ports. this is a consequence of the additional circuitry required to support the bidirectional feature on port c. figure 42. output ports for input and bidirectional ports, the termination structure consists of two 54.5 resistors connected to a termination supply and an 1173 resistor connected across the differential inputs, the latter being a result of the finite differential input impedance of the equalizer. ac coupling one way to simplify the input circuit and make it compatible with a wide variety of driving devices is to use ac coupling. this has the effect of isolating the dc common-mode levels of the driver and the AD8159 input circuitry. ac coupling requires a capacitor in series with each single-ended input signal, as shown in figure 43 . this should be done in a manner that does not interfere with the high speed signal integrity of the pcb. 05611-042 50 ? 50 ? v cc v cc 54.5 ? v tti /v ttio driver AD8159 54.5 ? vee 1173 ? c p c n ip in figure 43. ac-coupling input signal of AD8159
AD8159 rev. a | page 20 of 24 dc coupling when ac coupling is used, the common-mode level at the input of the device is equal to v tti . the single-ended input signal swings above and below v tti equally. the user can then use first, consider the dc-coupled case (see figure 44 ). a lane on output port a or output port b on the AD8159 is dc-coupled to a receiving device. in this example, the output termination voltage (v tto ) on the AD8159 is set to the same level as the input termination voltage (v ttir ) on the receiving device, and this level sets the high value (v hi ) of the single-ended output voltage. with pre-emphasis low (pe = 0), the maximum single- ended current is 16 ma figure 22 and figure 25 to determine the acceptable range of common-mode levels and signal swing levels that satisfy the input range of the AD8159. if dc coupling is required, determining the input common- mode level is less straightforward because the configuration of the driver must be also be considered. in most cases, the user would set v tti on the AD8159 to the same level as the driver output termination voltage, v ttod . this prevents a continuous dc current from flowing between the two supply nets. as a practical matter, both devices can be terminated to the same physical supply net. 1 , which flows through the parallel combination of the 50 on-chip resistor and the 50 far end termination. therefore, the low value (v lo ) of the output voltage is equal to v tto ? 16 ma ( 50 || 50 ) = v tto ? 400 mv because the minimum allowed voltage at the output is v cc ? 1.6 v, the lowest acceptable value for v tto is consider the following example: a driver is dc-coupled to the input of the AD8159. the AD8159 input termination voltage (v tti ) and the driver output termination voltage (v ttod ) are both set to the same level; that is, v tti = v ttod = 3.3 v. if an 800 mv differential p-p swing is desired, the total output current of the driver is 16 ma. at balance, the output current is divided evenly between the two sides of the differential signal path, 8 ma to each side. this 8 ma of current flows through the parallel combina- tion of the 54.5 input termination resistor on the AD8159 and the 50 output termination resistor on the driver, resulting in a common-mode level of v cc ? 1.6 v + 0.4 v = v cc ? 1.2 v increasing pre-emphasis to its highest level (pe = 3) results in a maximum, single-ended current of 28 ma. in this case 2 v lo = v tto ? 28 ma (50 || 50 ) = v tto ? 700 mv as a result, the lowest acceptable value for v tto is v cc ? 1.6 v + 0.7 v = v cc ? 0.9 v it is expected that the minimum v tto is 300 mv higher than the case when pe = 0, because incr easing the pre-emphasis level results in a 300 mv lower voltage excursion at the output. v tti ? 8 ma ( 50 || 54.5 ) = v tti ? 209 mv the user can then use figure 25 to determine the allowable range of values for v tti that meets the input compliance range based on an 800 mv p-p differential swing. 1 the output current for port c when pe_c = 0 is slightl y higher, 20 ma. the extra 4 ma of current (compared to port a/port b) is needed to support the bidirectional feature. output compliance 2 the output current for port c when pe_c = 3 is 32 ma, for the same reason as stated in endnote 1. not surprisingly, there is also a range of voltages that satisfies the requirements of the output devices. this range is specified as the minimum and maximum voltage (with respect to v cc ) allowed at an output pin. 05611-043 50 ? 50 ? v tto v ttir AD8159 receiving device op on port a/b: (16 + 4 pe) ma port c: (20 + 4 pe) ma v ee figure 44. dc-coupling output signal from AD8159
AD8159 rev. a | page 21 of 24 ac coupling in general, more v tto supply headroom is required with ac- coupled outputs. when the outputs are ac-coupled, the average single-ended current does not see the far end 50 termination because the capacitor acts as a dc block. for example, with pe = 0, the single-ended output current alternates from 0 ma to 16 ma, or 8 ma on average. this 8 ma current flows entirely through the on-chip 50 termination resistor due to the dc block. the single-ended output voltage has an average value of v tto ? 8 ma 50 = v tto ? 400 mv for appropriate data patterns, 1 the capacitor acts as a short and the voltage swing is 400 mv p-p, identical to the dc-coupled case. the low output voltage is, therefore, v tto ? 400 mv ? 200 mv = v tto ? 600 mv 1 ac coupling requires that the signal pattern have no long term dc component. codes such as 8b/10b, for example, ensure that the data pattern is benign in an ac-coupled link. the lowest acceptable value for v tto is v cc ? 1.6 v + 0.6 v = v cc ? 1.0 v the same exercise can be repeated for other pre-emphasis settings. output compliance table to simplify the task of interfacing to the AD8159 output, table 13 is useful as a quick-reference. it provides the minimum and maximum values for output termination voltage for both ac and dc coupling. the values in the table are valid for any pre- emphasis setting. table 13. output compliance ac-coupled dc-coupled minimum (v) maximum (v) minimum (v) maximum (v) v tto v cc C 0.5 v cc + 0.6 v cc C 0.9 v cc + 0.6 v ttoi v cc C 0.4 v cc + 0.6 v cc C 0.8 v cc + 0.6
AD8159 rev. a | page 22 of 24 outline dimensions compliant to jedec standards ms-026-aed-hd 1 25 26 50 76 100 75 51 14.00 bsc sq 16.00 bsc sq 0.75 0.60 0.45 1.20 max 1.05 1.00 0.95 0.20 0.09 0.08 max coplanarity view a rotated 90 ccw seating plane 0 min 7 3.5 0 0.15 0.05 view a pin 1 top view (pins down) 0.27 0.22 0.17 0.50 bsc lead pitch 1 25 26 50 76 100 75 51 bottom view (pins up) 5.00 sq exposed pad notes 1. center figures are typical unless otherwise noted. 2. the AD8159 has a conductive heat slug to help dissipate heat and ensure reliable operation of the device over the full industrial temperature range. the slug is exposed on the bottom of the package and electrically connected to v ee . it is recommended that no pcb signal traces or vias be located under the package that could come in contact with the conductive slug. attaching the slug to a v ee plane will reduce the junction temperature of the device which may be beneficial in high temperature environments. 040506-a figure 45. 100-lead thin quad fl at package, exposed pad [tqfp_ep] (sv-100-4) dimensions shown in millimeters ordering guide model temperature range package description package option AD8159asvz ?40c to +85c 100-lead tqfp_ep sv-100-4 1 AD8159-eval-dc ?40c to +85c dc -coupled evaluation board AD8159-eval-ac ?40c to +85c ac -coupled evaluation board 1 z = pb-free part.
AD8159 rev. a | page 23 of 24 notes
AD8159 rev. a | page 24 of 24 notes ?2006 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d05611-0-4/06(a)

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